1. Field of the Invention
The present invention relates to a method for manufacturing a Semiconductor Memory. The present invention is used, for example, in the manufacture of EEPROMs (Electronically Programmable Read Only Memories).
2. Description of Related Art
EEPROMs are a commonly known type of nonvolatile semiconductor memory. In the most generally known EEPROM, a single memory cell comprises a single memory transistor and a single selector transistor. A transistor with a floating gate is used as this memory transistor.
FIG. 1 is a circuit diagram showing an exemplary constitution of an EEPROM memory cell. The EEPROM shown in FIG. 1 is provided with the memory transistor 101 and the selector transistor 102. The source of the memory transistor 101 and the source of the selector transistor 102 are connected.
FIGS. 2A and 2B are conceptual diagrams of an exemplary constitution of the memory cell shown in FIG. 1. FIG. 2A is a plan diagram and FIG. 2B is a diagram of a section along the line A-Axe2x80x2 in FIG. 2A.
As shown in FIGS. 2A and 2B, memory transistor 101 is provided with drain 202, source 203, gate oxide film 204, tunnel window 205, floating gate 206, ONO film 207 and controller gate 208. Drain 202 and source 203 are formed by doping an impurity such as arsenic into the surface of the silicon substrate 201. The tunnel window 205 is formed by exposing the surface of the source 203 through the removal, by etching, of part of the gate oxide film 204, and by forming a thin oxide film (in other words tunnel oxide film) 204a to permit the electric current to flow on this exposed surface.
In addition, as shown in FIGS. 2A and 2B,the selector transistor 102 is provided with drain 209, source 210, gate oxide film 211 and gate 212. The drain 209 and the source 210 are formed by doping an impurity such as phosphorus into the surface of the silicon substrate 201. The drain 209 and the source 210 respectively comprise shallow regions Nxe2x88x92 and deep regions N+. In FIG. 2B, shallow region Nxe2x88x92 is indicated by a broken line and deep region N+ by a solid line. Gate 212 is formed from polysilicon, for example.
To give an EEPROM a high degree of integration, it is necessary to make the dimensions of the memory cells small. To make the dimensions of the memory cells small, it is preferable to position the memory cells with high accuracy during manufacture. This is because, if the dimensions are made small even though positioning accuracy is low, the EEPROM yield declines owing to the influence of positioning offsets. It is preferable to specify the memory cell dimensions in a way that allows positioning offsets at the manufacturing stage. For example, if the design rule is 0.5 xcexcm, the maximum value of the position offset of the layers in the photolithography process becomes 0.2 xcexcm per layer. Therefore, in the EEPROM shown in FIG. 2A and FIG. 2B, if the source 203 and tunnel window 205 are formed by different photolithography processes, the corresponding positioning offset between source 203 and tunnel window 205 (in other words the manufacturing error which is the distance L1 shown in FIG. 2B) becomes at maximum 0.4 xcexcm. In this case, the position and dimensions of the source 203 must be specified in such a way that a 0.4 xcexcm error is allowed. For reasons such as this, increasing the degree of integration of an EEPROM requires technology for increasing the positioning accuracy at the time of manufacture.
In addition, when the tunnel window is formed, in the prior art, it was not possible to make the diameter L2 of the tunnel window (see FIG. 2B) smaller than the photolithography resolution limit. This becomes an impediment to increasing the integration of an EEPROM. Therefore, in order to increase the degree of integration of an EEPROM, it is desirable to be able to use a technique which allows a tunnel window to be made with a diameter which is smaller than the photolithography resolution limit.
One of the objects of the present invention is to eliminate the influence of a positioning offset in the photolithography process.
Another object of the present invention is to make the diameter of the tunnel window smaller than the photolithography resolution limit.
For this reason, the method for manufacturing a Semiconductor Memory to which the invention relates comprises steps of: forming a gate insulator film on the surface of a semiconductor substrate; forming a mask layer comprising through-holes at positions where tunnel windows are to be formed, on top of said gate insulator film; forming an impurity region in the vicinity of the surface of said semiconductor substrate by doping an impurity using the mask layer; and forming a tunnel insulator film on the surface of said semiconductor substrate, using the mask layer.
In the present invention, the position for forming the impurity introduced region and the position for forming the tunnel window are determined by means of the position of the same through-hole. Therefore the manufacturing error in the distance between the impurity introduced region and the tunnel window can be nullified.
In addition, in the present invention it is preferable if, before the step for forming an tunnel window, there is further provided a step for forming a side wall on the inner wall of the through-hole.
By forming a side wall on the surface of the inner wall of the through-hole, it is possible to make the diameter of the tunnel window smaller than the photolithography resolution limit.